DESIGNING A CMOS LOGIC CIRCUIT

Grading Policy of the Project:

Magic Layout: (75/100)
1. Function (combinational logic) (35/100)
2. Layout (minimum area & reducing parasitic R,L & C) (15/100)
3. Glitch free (4 points reduction for every 1 volt additional glitch) (15/100)
4. VOH & VOL (NMH & NML) (10/100)
Considering VDD=5V for case 3 & 4
Report: (25/100)
1. Introduction, gate configuration and combinational logic circuit design (9/100)
2. Print of the IC layout & SPICE simulation (6/100)
3. Analysis for glitches & possible low VOH & high VOL (trouble shooting procedures) (5/100)
4. Conclusion (3/100)
5. Format (2/100)

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Last updated: 01-May-2002